Current demands for high density and performance associated with ultra large scale integration require aggressive scaling (i.e., shrinking) of design rules, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Metal oxide semiconductor (MOS) devices, as depicted in FIGS. 1a and 1b, are the building blocks of today's circuits, and typically comprise a pair of source/drain regions 110 formed, as by ion implantation, in a silicon substrate 100, and separated by an ion-implanted channel region 120. A gate oxide layer 130 is formed above channel region 120, and a conductive gate 140, such as a polysilicon gate, is formed on gate oxide layer 130. Gate 140 is typically formed by depositing a blanket layer of polysilicon, masking the polysilicon layer with a patterned photoresist mask, and etching the polysilicon layer. Gate 140 is typically a narrow polysilicon line that runs completely across the width W of source/drain regions 110 and channel region 120 (called the "bulk silicon region"), and has a width L, commonly referred to as "gate length".
The performance of MOS transistors is significantly affected by gate length L. For example, the current output of the transistor is proportional to W/L. Thus, a smaller gate length L will result in a higher-performance transistor per unit width of the bulk silicon region. As a result, newer circuit designs include increasingly smaller gate lengths; for example, a gate length of about 150 mn or less for a device having a design rule (i.e., minimum feature width) of about 180 nm. However, this aggressive reduction in gate length makes gate formation more difficult, due to the limitations of the photolithographic process.
Transistors such as those shown in FIGS. 1a and 1b have distinct "on" and "off" states. It is important for device performance to have a minimum amount of current flow, known as "leakage current", between source/drain regions 110 when the device is off (ideally, no current should flow). To effectively control the leakage current during its off state, transistor gate 140 must span or "strap" the entire width W of the bulk silicon region. To ensure that the gate length meets this requirement after processing, gate 140 must be photolithooraphically formed ("drawn") to extend beyond the width W of source/drain regions 110. The portions 140a of gate 140 that extend beyond width W are called "gate endcaps". Historically, to provide for a margin against possible layer-to-layer misalignment between the definition of transistor source/drain regions and the polysilicon gate, the end cap has been drawn at about half a feature size (i.e., about 250 nm for 0.5 micron technology).
Disadvantageously, as feature size is scaled below about 250 nm, a phenomenon known as "pullback" occurs during lithographic printing of the narrow gate image onto the photoresist layer, and during subsequent etching of the polysilicon film. FIG. 2A depicts a reticle 200 employed to "print"(i.e. expose using a stepper) a photoresist mask on a blanket polysilicon layer 210 that has been deposited over source/drain regions 110 and channel region 120. Reticle 200 has a chrome feature 200a of the desired size of gate 140, including endcaps 140a of design rule length.
FIGS. 2B and 2C illustrate typical results of the photolithographic printing process. In FIG. 2B, wherein the gate length L (i.e., the width of chrome island 120) is substantially larger than the exposing wavelength (typically about 248 nm for current technology), the printed gate image 220 matches the drawn geometry of chrome island 120 very well, with only minor corner rounding due to well-known optical properties. The extent of the corner rounding is small compared to the gate length L. However, as gate length is scaled towards or below the exposing wavelength, as illustrated in FIG. 2C, the printed endcap tip is significantly modified. The tip is completely rounded and exhibits endcap shortening known as "pullback". The amount of pullback increases with smaller gate lengths relative to the exposing wavelength, with increased exposing energy and with subsequent etching. Tip rounding and tip pullback necessitate that additional margin be built into the endcap design rules.
FIG. 2D illustrates four possible gate and endcap configurations after final processing, two of which (gates 220a and 220b) are adequate, and two of which (gates 220c and 220d) reflect unacceptable endcap design. To minimize transistor off state leakage, it is not sufficient to guarantee that the endcap straps the entire width W of the transistor (i.e., it is not sufficient to simply provide a margin against misalignment and pullback). The endcap must be of sufficient length to extend beyond the transistor width, since if the gate has a rounded portion within the transistor width, as in gate 220c, the rounded portion will contribute to increased off state leakage. Thus, as the design rule for the transistor is scaled, the endcap design rule must be increased to maintain an acceptable margin against off state leakage. For example, the endcap design rule for a 180 nm device design rule is typically 1.5.times. minimum feature size, which is far larger than the 0.5.times. minimum feature size design rule used on earlier technologies. Thus, for each global design rule shrink, the endcaps need to be redrawn, thereby increasing manufacturing costs.
A conventional technique to reduce pullback is to form larger endcaps 140a, such as by adding so-called "hammerheads" to their tips. However, due to space constraints on substrate 100 between endcaps of neighboring devices and between endcaps and other features on the substrate (such as conductive polysilicon lines and metal lines), the size of the hammerheads must be limited, decreasing their effectiveness, or the features on the substrate must be undesirably spaced farther apart than the minimum spacing allowed under the design rules, thereby decreasing transistor density. There exists a need for a methodology for reducing or eliminating gate endcap pullback, thereby enabling increased transistor density, reducing manufacturing costs and improving device performance.